Gate stack technologies for SiC power MOSFETs

渡部 平司*; 細井 卓治*; 桐野 嵩史*; 上西 悠介*; Chanthaphan, A.*; 池口 大輔*; 吉越 章隆; 寺岡 有殿; 箕谷 周平*; 中野 佑紀*; et al.

ECS Transactions, 41(3), p.77 - 90, 2011/00

https://doi.org/10.1149/1.3633023

It is well known that SiC-based MOS devices have suffered from degraded electrical properties of thermally grown SiO/SiC interfaces, such as low inversion carrier mobility and deteriorated gate oxide reliability. This paper overviews the fundamental aspects of SiC-MOS devices and indicates intrinsic obstacles connected with an accumulation of both negative fixed charges and interface defects and with a small conduction band offset of the SiO/SiC interface which leading to the increased gate leakage current of MOS devices. To overcome these problems, we proposed using aluminum oxynitride insulators stacked on thin SiO underlayers for SiC-MOS devices. Superior flatband voltage stability of AlON/SiO/SiC gate stacks was achieved by optimizing the thickness of the underlayer and nitrogen concentration in the high-k dielectrics. Moreover, we demonstrated reduced gate leakage current and improved current drivability of SiC-MOSFETs with AlON/SiO gate stacks.